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1. 

   Zouk
   Member

   I've been poking around for this figure and haven't had much luck, and I've been reluctant to poke at the board with a DMM because I'm not sure what voltage I'm going to be exerting on the IO pin. Paranoid, I know.

   I've looked at the datasheet (http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATASHEET/CD00161566.pdf) and found two figures of note:

   Rain - External Input Impedence - This is listed as 50kOhms, but based on other things in the datasheet, this seems like this is the maximum external signal impedance to ensure ADC accuracy.
   Radc - Sampling Switch Resistance - This is listed as 1kOhm, but I've no earthly idea what that means.

   I'd looked into measuring voltage across a capacitor that theoretically was charged to 9V (so that I can notice a drop and save settings before power is lost), but when I calculated what values I'd probably need, I wouldn't get results that made any sense (4095 even if I twiddled the adjustment pot so that I'd get less than 3.3V).

   So, when I'm trying to put together a voltage divider to move the range of a signal voltage to something that the Maple can survive, should I be taking into account the input impedance of the ADC? Am I just going about this completely wrong?

   Posted 3 years ago #
2. 

   gbulmer
   Moderator

   Zouk - Here's my way of thinking, I hope it helps.

   Table 47 explains the relationship between the output impedance of the upstream circuit (the signal source and voltage divider), and the sampling time.

   How fast do you need to measure the signal?

   Once you know that, you can estimate the maximum sample time, ts(us), in Table 47, and from that you can get the maximum impedance of the upstream signal, Rain(max).

   This impedance is a combination of the output impedance of the signal source plus the voltage divider.

   As a first approximation, treat the voltage divider as a resistance in series with the source signal.

   If the signal is just a battery, it's impedance is likely negligible, so then ensure the voltage divider is low enough to be less than Rain for the sampling frequency you need.

   If the upstream signal has a non-negligible output impedance, subtract that from Rain(max) (for the corresponding sampling rate you need), and you have an estimate for the total impedance of the voltage divider.

   Note, by default, the Maple ADC is driven by a 12MHz clock, and it is configured to sample for 55.5 cycles. So multiply the ts(us) 14MHz/12Mhz.

   Posted 3 years ago #

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