youthreewire
Member
Hi,
I am thinking of getting the ADC run at 14 Mhz which gives a conversion and sampling time of 14 x 1/Fadc as per the data sheet.So the acquisition time should be about 1uS. Also I want to set the ADC in 10 bit mode and the maximum voltage to be measured is 5V. Is this possible with the default settings on Maple STMF103?
Thanks
(Maple newbie)
StephenFromNYC
Moderator
September 6, 2010
Hello youthreewire-
If your code is not too long it may be better easier for uses to read and comment if you include the code using the "blockquote" markup tag..
Check out these suggestions for faster ADC conversion.
http://forums.leaflabs.com/topic.php?id=154#post-1001
I have been busy the last few days, so I have not been able to test the modified code.
Good luck,
Stephen from NYC
poslathian
LeafLabs
A few notes about the ADC:
1) It is true that stm32 on Maple supports two channels at 12bit, 1MHz sampling rate, and can be multiplexed out to 16 channels.
2) The current ADC library implementation in wirish is rather naiive, and due to configuration and overhead, consecutive calls to analogRead give about 130KHz sampling rate. The ADC's are VERY difficult to configure, so wirish just gives you a simple setup that works - but doesnt pull the full performance. Expanding the configuration options for ADC's is definitely high on our stack, if you have fooled with alternative configurations, let us know!
3) We recently discovered, that when running the stm32 at 72MHz (Maple default) the ADC's actually max out at 800+KHz, not the full 1MHz. If you slow the clock down, you can get the full 1MHz. I dont know all the details on this issue, but apparently is buried somewhere in the documentation. We will fix our docs to reflect this. Slowing down the system clock to max out the ADC's falls under the category of "improvements to the wirish adc interface"
4) I know of one user who made a minor mod to the adc code in libmaple to get much faster sampling than the 130KHz - enough to decimate 44KHz audio 8 times and get ~16 bits! I will try and track down this change and post.
poslathian
LeafLabs
A suggestion from okie - in adc.c (in libmaple if youre a terminal dev person, or in hardware/leaflabs/cores/maple if youre working in the IDE:
change ADC_SMPR1 and ADC_SMPR2 to 0. This should get the ADC's running at the 800KHz+ level minus whatever function call overheads you incur when you call analogRead. While I have not benchmarked or verified this change, I have heard very high quality audio passthrough when decimating analogRead 8 times in a loop to up the bitdepth from 12 to about 16.
gbulmer
Moderator
youthreewire - I had believed that 10bit was possible.
I combed through the ADC section in the RM0008 Reference Manual (document 13902 from st.com), and I can't find any mention of a 10-bit mode. I currently think there is no 10-bit mode, so if you find it, please post in the forum.
I did see that there is a 12-bit or 8-bit mode on the 'high-density family' DAC, so until now, I had assumed that was confusing me. You having the same belief (10-bit mode) has caused me to start to look again.
There is a 'fast interleaved' mode, which uses two ADC's to sample the same signal alternately. So one starts to sample, then the 2nd one starts 7 ADC clock cycles later, the first one finishes 7 cycles later, and can immediately start again, and so on. This is described as giving 2x the sample+conversion rate of one ADC. It's described in section "11.9.3 Fast interleaved mode", page 229, of RM0008. So, in theory, it should sample at about 1.7M samples/second on a Maple, with no other changes. Ten-bit samples would only save a couple of clock cycles, this is more significant.
If the processor-clock speed is dropped from 72MHz to 56MHz, and the ADC-clock prescaler decreased to 4 (to get 14MHz), then a single ADC should give 1Msamples/second, and Fast-Interleave theoretically gives 2M samples/second, at 12-bits/sample.
Note: this is all contingent on the quality of the source of the signal being sampled. If it is high-impedance (the adc.c code comments suggest it needs to be under 0.4k), then the signal can not drive the sample input of the ADC anywhere near these rates anyway. The sample time will rapidly dominate the sample+conversion time.
I have not tried any of that, but intend to. I would like to reach better than 1.6M samples/second for a possible project.
poslathian
LeafLabs
good point gbulmer, we have seen empirically that impedance mismatch KILLS the ADC. Follow the guidelines in the documentation (either ST or ours) to make sure your input signal is of appropriate impedance for your desired sample rate.
EDIT: "mismatch" is probably the wrong word there, since "impedance mismatch" means something specific related to transmission lines. Hopefully you know what i meant.
gbulmer
Moderator
I am not an Electrtonics Engineer, but I believe the appropriate phrase is "output impedance of the signal source". This amounts to the amount of current the signal source can supply (without significant distortion). The source output impedance can be significantly improved quite cheaply using a well-chosen operational amplifier (Op Amp).
I would highly recommend the jaw-droppingly brilliant "The Art of Electronics, second edition" by Horowitz and Hill (e.g. http://www.amazon.com/Art-Electronics-Student-Manual-Exercises/dp/0521377099/ref=tmm_other_title_0?ie=UTF8&qid=1284075647&sr=8-1)
PS - AFAIK, I have no commercial or personal relationship with Horowitz or Hill
[Except, of course through the "6 degrees of separation", which may be a bit shorter than average for me simply because I lived and worked in Cambridge MA for a while.]
mbolivar
LeafLabs
It seems there's some agreement here at the lab :)
http://imgur.com/F6hO8.jpg
(Although I myself am emphatically not an electronics engineer)
gbulmer
Moderator
mbolivar - Thank you!
I wasn't at all sure when I first read you post whether you meant the lab was agreeing with my assertion that "I am not an Electronics Engineer", or "I have no ... relationship with Horowitz or Hill", or ... (They were all funny, though :-)
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