a little FPGA learning progress to report. I started with some basic tutorials, mainly from Digilent's website, to create a basic gate, synthesize it, map and route it into the chip, and create the the bit file for downloading. Next was learn Adept, Digilent's free tool for downloading bit files into the device on the dev board. Pretty straight forward, but you learn pretty quickly where and how to set CCLK to J-TAG CLK in WebPack.
There are lots of WebPack tutorials out there, some from Digilent, some from Xilinx, and some from Universities - all are free, and all reference a WebPack version from the past. Consequently, you can't just follow along; you have to figure out how to accomplish the same goal using version 13.1. Not a bad thing, I guess, as you actually need to understand the process and the step you are trying to take to get it to work. The biggest differences with 13.1 and previous seem to be Navigator tabs and other layouts, Workbench test creation, the simulator, and creating User Configuration Files (ucf). 13.1 uses ISIM lite for the simulator, which is different from the past, probably different to the full version in the full ISE, and definitely different to the various versions used in tutorials. It's quite capable, but you are definitely on your own learning how to use it. Workbench tests seem dramatically different from the past where the wizard appeared to give you a waveform editor to create your test. 13.1 gives you a VHDL module pre-filled with essential stuff, but you have to code your own test process. Once you get it syntax correct, you can use it to open your ISim module and then you have your waveform. Want to change something, back to VHDL.
To run the design process, you have to have a user constraints file to map your signals to FGPA I/O pins. WebPack 13.1 uses the Plan Ahead tool to do this graphically, but I have found this not to be overly useful. For myself, and I suspect the majority of the Leaflabs community, we are not designing a new system using a FPGA; we are using an FPGA that is part of an existing system, such as Oak or a FPGA dev board. Consequently, many (all??) of the FGPA I/O pins are already assigned to other components on the board, such as peripheral connectors etc. My Nexys 2 board for instance, provides connections to 8 switches, 8 leds, 4 push buttons, a 4 digit/7 segment display, a VGA port, a RS-232 Port, a PS2 port, the USB port, 4 x 12pin peripheral connectors, and a 40 pin expander board connector. So the ucf I use is the one I downloaded from Digilent for the Nexys 2, and I copy that into all my WebPack projects. I edited all the NET lines to comments so that I can enable only the connections I am using in this project...and it's way easier to deal with using a text rather than a graphics editor.
Which brings up an interesting issue, and maybe one reason Oak seems slow in appearing. Other than the Nexys 2 ucf, I don't have to include anything else; the FPGA belongs to me and I can make use of what it and Digilent provides as board hardware any way I choose. Leaflabs is producing a system in which the FPGA is a component. As part of the Oak system, I'm sure Leaflabs has specific (what do you call this stuff, files, code ...) files that are loaded in the FPGA that help make the overall system work. Anything new loaded into the FPGA will need to incorporate the LeafLab suite, and be compatible with same. Oak is orientated towards the hobbyist community, not EEs, so this integration process needs to be foolproof yet easy to use, otherwise LeafLabs will spend all their time in support and handholding, not creating the wonderful new toys we all wanted from them yesterday. Yet, this is not a simple process, synthesis and design mapping, routing and performance tuning is a complex area totally dependent on the specific flavor of FPGA being used; something only the FPGA manufacturer is able to do well. So, I imagine LeafLab's challenge is how to come up with an easy-to-use yet foolproof tool chain that automatically includes what LeafLab needs into in the build so that the system is not compromised, yet still use Xilinx XPS and other design suite tools to make sure the FPGA is used efficiently.
When you buy a dev board from Digilent you have the option to bundle it with a "how to" text book and save a few bucks on the individual purchase. The book I chose was "Digital Design Using Digilent FPGA Boards", published by LBE Books. This is all about VHDL. You can certainly use the WebPack schematic editor and the library of packaged logic components to create meaningful solutions, but you can only tap a small portion of the FPGA capability that way. So, if you are serious, VHDL or Verilog and boolean algebra are in your future. This book had me knee deep in boolean algebra and K charts by Chapter 2; I tried skipping over it all, even though I once knew all this stuff, because now it just makes my head hurt; but no way, there is no alternative to knowing and understanding this topic if you are going to design efficient logic circuits.
I have worked my way through into Chapter 5 where I just created a circuit to display the hex value of the switches 0-3 on the 7 segment display. When I first ran it, the display looked like chinese. I even did the K-Chart from truth table exercise, so I was sure the logic was right, and the simulator said that I was correct. I was selecting the right segments for each character, but not according to the board. Then I looked at how Digilent defined the 7 segments in the ucf, and yes, they were in the reverse array order to VHDL's "6 downto 0" vector assignment. Some ucf editing and Bob's your uncle :-).
Now for a Clock Divider project to add to the seven segment display so I can display a 16 bit hex value and accomplish something I hope results in my first "keeper" project.
