LeafLabs Garden » Topic: Oak FPGA Toolchain

LeafLabs Garden » Topic: Oak FPGA Toolchain http://forums.leaflabs.com/topic.php?id=62 A place to share, learn, and grow... en-US Fri, 22 Jan 2016 00:00:46 +0000 http://bbpress.org/?v=1.0.2 <![CDATA[Search]]> q http://forums.leaflabs.com/search.php gbulmer on "Oak FPGA Toolchain" http://forums.leaflabs.com/topic.php?id=62&page=5#post-105766 Thu, 06 Aug 2015 04:58:12 +0000 gbulmer 105766@http://forums.leaflabs.com/ @mian2zi3 - Sorry for the slow response, and big thanks to you and Clifford Wolf for the wonderful work, and you for the Update. I had pretty much assumed there wouldn't be an Open Source FPGA toolchain in the near future, so this is a very pleasant surprise. Even better, the <a href="http://www.latticesemi.com/icestick">iCEstick Evaluation Kit</a> FPGA development hardware is quite reasonably priced, with <a href="http://www.latticestore.com/searchresults/tabid/463/searchid/1/searchvalue/ice40hx1k-stick-evn/default.aspx">Lattice selling it at $21.86</a> For anyone interested, I did a quick check, and it is available in the UK at: <a href="http://uk.mouser.com/ProductDetail/Lattice/ICE40HX1K-STICK-EVN/?qs=%2fha2pyFadugY4woXwsBFcG4ricvRE8gsBJ8rWqbssc4%3d">Mouser UK for £14.54+VAT</a> <a href="http://uk.farnell.com/lattice-semiconductor/ice40hx1k-stick-evn/ice40-hx1k-icestick-eval-kit/dp/2355207?ost=iCEstick">Farnell UK for £19.22+VAT</a> Thank you very much for the Update. (Full disclosure: I am not a member of LeafLabs staff.) mian2zi3 on "Oak FPGA Toolchain" http://forums.leaflabs.com/topic.php?id=62&page=5#post-105764 Sun, 26 Jul 2015 22:57:58 +0000 mian2zi3 105764@http://forums.leaflabs.com/ This isn't directly relevant to Oak, but my be interesting in the larger context of the conversation. There is now a complete, open source, Verilog-to-bitstream toochain for one family of FPGAs, the Lattice iCE40. Reverse engineering and tools to generate bistreams was done by the IceStorm project. Yosys is an open source Verilog synthesis tool. (Both done by Clifford Wolf.) I wrote a place and route tool (simulated annealing placement with multi-pass congestion aware routing) targeting IceStorm and the iCE40. Here are some links: <a href="http://www.clifford.at/icestorm/" rel="nofollow">http://www.clifford.at/icestorm/</a> <a href="https://github.com/cseed/arachne-pnr" rel="nofollow">https://github.com/cseed/arachne-pnr</a> <a href="http://www.clifford.at/yosys/" rel="nofollow">http://www.clifford.at/yosys/</a> codelectron on "Oak FPGA Toolchain" http://forums.leaflabs.com/topic.php?id=62&page=5#post-105276 Tue, 11 Mar 2014 15:27:41 +0000 codelectron 105276@http://forums.leaflabs.com/ Hi Guys, This post is about open source fpga toolchain. I have been searching about this topic for many months or years and I found a solution which should work although I havent tested it myself. I have written about it in my blog <a href="http://www.codelectron.blogspot.de/2014/03/open-source-fpga-tool-chain.html" rel="nofollow">http://www.codelectron.blogspot.de/2014/03/open-source-fpga-tool-chain.html</a> .I know that the last post was two years back but I wanted to continue that from here rather than creating a new topic. May be this is useful for Oak or may be its not. let me know about your opinions on my findings. Krishna <a href="http://www.codelectron.com" rel="nofollow">http://www.codelectron.com</a> pra on "Oak FPGA Toolchain" http://forums.leaflabs.com/topic.php?id=62&page=5#post-5716 Sat, 23 Jul 2011 10:25:11 +0000 pra 5716@http://forums.leaflabs.com/ Taking a break from FPGA for a few days to let my poor brain settle a bit. I've become fairly fluent with WebPack and its features. It's definitely a good product and straightforward to use, but there is so much to learn about the FPGA process. I have completed working my way through the "Digital Design" book and implemented all of the examples I cared to. The most sophisticated was getting the 4 digit 7 Segment display on the Nexys 2 to scroll out my cell phone number. I have become moderately competent in VHDL and have created a number of designs of my own in VHDL from scratch. Given all I have had to learn (and must still learn) about FPGA design and usage, learning VHDL was a minor undertaking, one that I feel absolutely necessary if you intend to make use of the enormous capability of a FPGA. You can barely scratch the surface with the schematic approach. I did a couple Xilinx video tutorials on making efficient use of the Spartan 3 and found them helpful and logical. Armed with this knowledge, its been interesting to look at how the Synthesizer generates LUTs, Roms etc. based on my VHDL statements. For example, the tutorials suggest that "case" statements are the most efficient form of coding certain logic, and the synthesizer appears to turn these statements into a Rom built from block ram, maintaining the same pin to pin speeds, but using much fewer number of LUTs and slices. I have experimented with the Block Ram capabilities of the FPGA. Two options were available. BRams of various sizes are available via the Schematic Editor and the symbol library. These have no documentation and its difficult to tell exactly what all the signals are etc. without documentation. BRam can also be generated via the Core Generator. Here there is extensive documentation in the form of a comprehensive datasheet, and complete options to configure the device to what you need. It would appear that the Core Generator has superseded much of the symbol library, except for basic logic components. I tested my generated BRam with ISim by writing each cell's address to each cell's data storage, and then reading it back out. The test bench VHDL to do this was straightforward and it all worked beautifully. I recommend you bite the VHDL (or Verilog) bullet, because that is the only way to take advantage of the wealth of stuff Xilinx and partners make available. As mentioned before in this thread, the major challenge is understanding that this is not a sequential execution process like that with a normal language; everything happens instantaneously, simultaneously and continually. I have built a design that I have running with the ISim simulator and will test in the real world via my LCD display device (see different post). It is a 15 channel SPI interface, utilizing only MOSI, MISO, SCLK and four I/O pins on the microprocessor to select the 1-15 independent devices via Chip Select. I know I can basically build this with a 74HC154, but with the FPGA, I have niceties such as keeping all devices off the microprocessor I/O lines via tristate buffers until they have CS active etc. I have also made a 7 SPI device version, but the saving in microprocessor pins here is not as dramatic. pra on "Oak FPGA Toolchain" http://forums.leaflabs.com/topic.php?id=62&page=5#post-5655 Wed, 13 Jul 2011 14:24:09 +0000 pra 5655@http://forums.leaflabs.com/ a little FPGA learning progress to report. I started with some basic tutorials, mainly from Digilent's website, to create a basic gate, synthesize it, map and route it into the chip, and create the the bit file for downloading. Next was learn Adept, Digilent's free tool for downloading bit files into the device on the dev board. Pretty straight forward, but you learn pretty quickly where and how to set CCLK to J-TAG CLK in WebPack. There are lots of WebPack tutorials out there, some from Digilent, some from Xilinx, and some from Universities - all are free, and all reference a WebPack version from the past. Consequently, you can't just follow along; you have to figure out how to accomplish the same goal using version 13.1. Not a bad thing, I guess, as you actually need to understand the process and the step you are trying to take to get it to work. The biggest differences with 13.1 and previous seem to be Navigator tabs and other layouts, Workbench test creation, the simulator, and creating User Configuration Files (ucf). 13.1 uses ISIM lite for the simulator, which is different from the past, probably different to the full version in the full ISE, and definitely different to the various versions used in tutorials. It's quite capable, but you are definitely on your own learning how to use it. Workbench tests seem dramatically different from the past where the wizard appeared to give you a waveform editor to create your test. 13.1 gives you a VHDL module pre-filled with essential stuff, but you have to code your own test process. Once you get it syntax correct, you can use it to open your ISim module and then you have your waveform. Want to change something, back to VHDL. To run the design process, you have to have a user constraints file to map your signals to FGPA I/O pins. WebPack 13.1 uses the Plan Ahead tool to do this graphically, but I have found this not to be overly useful. For myself, and I suspect the majority of the Leaflabs community, we are not designing a new system using a FPGA; we are using an FPGA that is part of an existing system, such as Oak or a FPGA dev board. Consequently, many (all??) of the FGPA I/O pins are already assigned to other components on the board, such as peripheral connectors etc. My Nexys 2 board for instance, provides connections to 8 switches, 8 leds, 4 push buttons, a 4 digit/7 segment display, a VGA port, a RS-232 Port, a PS2 port, the USB port, 4 x 12pin peripheral connectors, and a 40 pin expander board connector. So the ucf I use is the one I downloaded from Digilent for the Nexys 2, and I copy that into all my WebPack projects. I edited all the NET lines to comments so that I can enable only the connections I am using in this project...and it's way easier to deal with using a text rather than a graphics editor. Which brings up an interesting issue, and maybe one reason Oak seems slow in appearing. Other than the Nexys 2 ucf, I don't have to include anything else; the FPGA belongs to me and I can make use of what it and Digilent provides as board hardware any way I choose. Leaflabs is producing a system in which the FPGA is a component. As part of the Oak system, I'm sure Leaflabs has specific (what do you call this stuff, files, code ...) files that are loaded in the FPGA that help make the overall system work. Anything new loaded into the FPGA will need to incorporate the LeafLab suite, and be compatible with same. Oak is orientated towards the hobbyist community, not EEs, so this integration process needs to be foolproof yet easy to use, otherwise LeafLabs will spend all their time in support and handholding, not creating the wonderful new toys we all wanted from them yesterday. Yet, this is not a simple process, synthesis and design mapping, routing and performance tuning is a complex area totally dependent on the specific flavor of FPGA being used; something only the FPGA manufacturer is able to do well. So, I imagine LeafLab's challenge is how to come up with an easy-to-use yet foolproof tool chain that automatically includes what LeafLab needs into in the build so that the system is not compromised, yet still use Xilinx XPS and other design suite tools to make sure the FPGA is used efficiently. When you buy a dev board from Digilent you have the option to bundle it with a "how to" text book and save a few bucks on the individual purchase. The book I chose was "Digital Design Using Digilent FPGA Boards", published by LBE Books. This is all about VHDL. You can certainly use the WebPack schematic editor and the library of packaged logic components to create meaningful solutions, but you can only tap a small portion of the FPGA capability that way. So, if you are serious, VHDL or Verilog and boolean algebra are in your future. This book had me knee deep in boolean algebra and K charts by Chapter 2; I tried skipping over it all, even though I once knew all this stuff, because now it just makes my head hurt; but no way, there is no alternative to knowing and understanding this topic if you are going to design efficient logic circuits. I have worked my way through into Chapter 5 where I just created a circuit to display the hex value of the switches 0-3 on the 7 segment display. When I first ran it, the display looked like chinese. I even did the K-Chart from truth table exercise, so I was sure the logic was right, and the simulator said that I was correct. I was selecting the right segments for each character, but not according to the board. Then I looked at how Digilent defined the 7 segments in the ucf, and yes, they were in the reverse array order to VHDL's "6 downto 0" vector assignment. Some ucf editing and Bob's your uncle :-). Now for a Clock Divider project to add to the seven segment display so I can display a 16 bit hex value and accomplish something I hope results in my first "keeper" project. BruceF on "Oak FPGA Toolchain" http://forums.leaflabs.com/topic.php?id=62&page=5#post-5617 Mon, 11 Jul 2011 14:34:47 +0000 BruceF 5617@http://forums.leaflabs.com/ Hey pra, thanks for posting. I don't go back quite as far as you but I do remember working with 300MB disk drives the size of washing machines and thinking 8" floppies were pretty spiffy, to use the technical term. Please do post your FPGA progress and your thoughts on Oak here, I'm interested in it too but I don't see a huge amount of discussion of the device lately. Any more tips like these on what resources you find useful for learning FPGA development are well appreciated, and hopefully I'll find some time to follow along at some point. Maple looks great, but it's a little like an Arduino on steroids. Oak is a different class of animal entirely. Maybe even a different phylum. pra on "Oak FPGA Toolchain" http://forums.leaflabs.com/topic.php?id=62&page=4#post-5615 Mon, 11 Jul 2011 13:24:29 +0000 pra 5615@http://forums.leaflabs.com/ This topic thread has been quiet for a while, so I thought I would try to liven it up. I got my first maple (I now have 4 of them) a few weeks ago and when I read that LeafLabs plans a Cortex M3 and Xilinx Spartan 3E FPGA on the same board (Oak) I got very excited about the prospects. To speed the learning curve and to get the old juices flowing about possibilities, I now have a Nexys 2 FPGA development board from Digilent (yah, I know the ChipKit people) with a Spartan 3E 500K gate FPGA in a 320 pin package. I have just started learning and playing with the development board using Xilinx's free WebPack toolkit and I think my experiences as I progress with this endeavor may be interesting and useful for thread readers. First off, a bit about myself. I am a semi-retired systems engineer who lives in a cabin on a mountain in WV (Almost Heaven West Virginia). Not the greatest place for high speed internet access; I'm about 500 meters beyond the max length of a DSL connection, and that combined with an ISP service oversold and underpowered bandwidth wise from the local communications company, leads to iffy and unreliable DSL connection. I have been in the IT industry for more years than I care to remember (> 40) and still work part-time as a security consultant to one of the nation's largest defense contractors. I started as a hardware field engineer on mainframes back in the late 1960s. Its amazing that the maple can probably outperform that original system (a Univac 494) which at the time ran the real-time reservation system for Australia's domestic airline, maybe many times over. If I still had the logic diagrams (and the patience), I could probably rebuilt that mainframe into my FPGA development board today with most of the capacity of the FPGA to spare. The capability and potential of what we have today is just incredible. Since those times I moved into software development, operating systems design, and eventually consulting. Moving onto WebPack. Some of the earlier comments in this thread regarding vendor tool chains; the 3.8 gigabyte download and my internet connection; and MS Windows only install had me a little skeptical and nervous. I used a Mac development environment. I run Windows 7 in a Parallels VM for windows stuff and I realize there are some useful tools out there that will only run in windows. Anyway, the WebPack download and install from Xilinx was smooth and painless. I downloaded their latest version (at the time) 13.1. They have a download manager that handled without trouble the restarts caused by two lost connections during 3 hour download. The install was easy and smooth, and registering and licensing of WebPack (free perpetual license) made simple via interactions with the Xilinx License Manager website. WebPack is a complex package of many different toolsets, but Xilinx has done a good job of knitting them all together using the ISE Navigator. Given the high version number, I don't imagine this has been a very easy or fast evolutionary process, but what they have today is pretty together and cohesive from a new user perspective. For the best perspective on the FPGA development process I recommend downloading the latest version of theSpartan3E_UserGuide from Xilinx. Starting at Chapter 13 "Using ISE Design Tools" is an amazing well-written (no engineer speak) and coherent walkthrough of the design and implementation process and how to accomplish it using Xilinx ISE tools, including WebPack. I think that will do it for now; as I progress further, I will add updates. The feeling of accomplishment from installing something as simple as a 8 input XOR circuit, and watching the Led turn on and off correctly as I set/reset switches on the Dev board is incredible. Off now to learn more about VHDL :-) josheeg on "Oak FPGA Toolchain" http://forums.leaflabs.com/topic.php?id=62&page=4#post-2633 Tue, 16 Nov 2010 15:43:42 +0000 josheeg 2633@http://forums.leaflabs.com/ It is a tough comparison next time you want to draw a circuit do you open eagle cad the non free and open source thingy. Or do you wine about using free and open source kicad. If you do then you want what you think is the easier way out. But if you like to type and think you can get that all correct and do not have a mouse plugged into your computer then shure type out the netlists I am shure it is scriptable... It took a very long time to write in the schematic capture schematic of something that might load info into my analog to digital converter. But it was some ands and or gates and shift registers and If I was to implement the BSS code to decode mucle signals it would be years. ... now if that was written in HDL it would be even longer... HDL makes asm look like something high level. Shure you can generate ands and or modules in hdl but if you had the ability to connect them by netlist by writing the netlist or drawing the modules. You had a choice. I agree UML models do not compile... I looked.... But schematics can connect to the board files and they can check eatchother. Also to say a schematic is not useful there used now and someone with a electronics background but not a perticular language can fallow the schematic. Also consider it documenting your code at the same time and how many bugs would be missed using a aplication or some other script to generate the schematic symbols in kicad to make it faster it is a toolsuete that is allready open source. So when you say what is faster this can be scripted and typed and graphical and document itself in pictures that are herarchal. Also the local and global pins etc are allready there in kicad so your structure is there. Also if the schematics were herarchal like in kicad then the HDL netlists woudl be like functions and classes with global and local pins like kicad has. Lava is described as netlisting using a text language so it is like nitting together a netlist using text once again. poslathian on "Oak FPGA Toolchain" http://forums.leaflabs.com/topic.php?id=62&page=4#post-2623 Tue, 16 Nov 2010 14:46:15 +0000 poslathian 2623@http://forums.leaflabs.com/ Ill have to check out gadgetfactory.org, that sounds interesting. icarus is a pretty successful open source verilog simulator. Im not sure how I feel about the python/c/c++/haskell -> verilog compilers. At least in the case of the c->verilog, performance is way down from hand coded verilog. Haskell->verilog has a decent open source project called lava, and a struggling commercial language called bluespec which is something like haskell+system verilog based around a programmers model of "guarded atomic actions" which is popular in the multicore world. I found it cumbersome. visual editing seems like a nice approach, but pro's really want to work with the keyboard, not the mouse - no one "writes" programs by "compiling" uml diagrams. Its really an open question of what direction to push FPGA devel in, and by the length of this topic I think its one that everyone is pretty excited to work on. josheeg on "Oak FPGA Toolchain" http://forums.leaflabs.com/topic.php?id=62&page=4#post-2569 Mon, 15 Nov 2010 16:29:07 +0000 josheeg 2569@http://forums.leaflabs.com/ Another way to look at things is if a schematic entery program geda or kicad I like kicad. Had basic logic and and or gates 2-3 of its libraries contained HDL info. Then something to parse the open netlist format kicad produced. To link the schematic drawings of the and and or gates and herarchy from a upper level sheet to a lower level sheet that looked like a chip sorta. Then verilog hdl could be output and that tool is open source as a simulator. Then you would use a vendor compiler. At least it gets it most of the way useable from high level to lower level rather than lower level to higher level. josheeg on "Oak FPGA Toolchain" http://forums.leaflabs.com/topic.php?id=62&page=4#post-2568 Mon, 15 Nov 2010 16:26:01 +0000 josheeg 2568@http://forums.leaflabs.com/ also I played with the open fpga design from gadgetfactory.org it even allowed for a arduino to be simulated. So you had pin configurable arduino with schematic fpga design using xilinx software. josheeg on "Oak FPGA Toolchain" http://forums.leaflabs.com/topic.php?id=62&page=4#post-2567 Mon, 15 Nov 2010 16:24:23 +0000 josheeg 2567@http://forums.leaflabs.com/ I looked into a lot of Myhdl and python created hdl and matlab created hdl. I tried using scilab or octave but the hdl link to eather of thowse is not avalable. The tool I did use was xilinx FPGA schematic drawing program and was going to make larger chip like modules from the drawn gates. You can see how if HDL files can be made into a schematic block then assebled together into schematic like diagrams a layored herarchal open source tool like kicad with its scriptablility for creating its schematic symbols & possibility for logic design I don't want to say geda and gnu cap for making digital logic simulatable then let it get packed into a fpga. Schematic versioning can get to be a pain. do the newest versions apaear with different color text? But kicad does have a herarchal design so if its netlist & standard and or etc a hand full of basic gates have the HDL logic behind them it might empower the linux community. gbulmer on "Oak FPGA Toolchain" http://forums.leaflabs.com/topic.php?id=62&page=4#post-2565 Mon, 15 Nov 2010 16:11:21 +0000 gbulmer 2565@http://forums.leaflabs.com/ So when is Oak intended to be available? poslathian on "Oak FPGA Toolchain" http://forums.leaflabs.com/topic.php?id=62&page=4#post-2558 Mon, 15 Nov 2010 15:43:49 +0000 poslathian 2558@http://forums.leaflabs.com/ Native is out for prototyping! Fingers crossed, were shooting to get it on sale in time to arrive at your doorstep by christmas. We had an annoying but AWESOME bug in the last prototype which required manually *skywiring* (go bryan) an entire 30 pin RAM bus to get everything to work. Perhaps Ill throw a picture of this up on the blog. mabl on "Oak FPGA Toolchain" http://forums.leaflabs.com/topic.php?id=62&page=4#post-2464 Sat, 13 Nov 2010 03:36:08 +0000 mabl 2464@http://forums.leaflabs.com/ There has been no git activity on maple native for two months now. Is Oak supposed to be released before Native? Is there any timetable out? I'm desperately waiting for the native...