Just to make sure I understand how 1_NSS is supposed to be handled when using spi channel 1....
I see in the GPIO pin maps for the Maple 5 that for spi channel 1, the assigned pins are:
D10 - 1_NSS
D11 - 1_MOSI
D12 - 1_MISO
D13 - 1_SCK
However, I'm also reading in the threads on SPI in this forum that HardwareSPI does _not_ manage 1_NSS at all, the program has to do that manually. Which is fine, but leads me to wonder: What is the significance of assigning D10 as 1_NSS? If it is an output that has to be managed manually, then _any_ available GPIO pin could be used as NSS?
Or have I missed something?
Thanks for any advice.