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1. 

   robodude666
   Member

   Howdy folks!

   I got my Maple in the mail today, along with some candy!

   I've started work on my first project, which requires me to control the data direction on the entire port. I see there is a gpio_set_mode function in libmaple for controlling the data direction of one gpio pin, but how do you set multiple at a time (for higher performance)?

   In my previous AVR world, you'd set DDRx to 0xFF or 0x00 to make it an output/input, etc. Is gpio->regs->CTL the closest thing? I see gpio_set_mode doing a few things, which confuse me. No 1-liner way of doing it?

   -robodude666

   Posted 4 years ago #
2. 

   snigelen
   Member

   Hello!

   There's some more options on the STM32 than on AVR and it's described in the reference manual (RM0008). But in short, there's four bits in a configuration register and, for pull-up/down, one bit in the ODR-register for each port pin.

   The two lower bits in the configuration register are (from RM0008)

   00: Input mode (reset state)
   01: Output mode, max speed 10 MHz.
   10: Output mode, max speed 2 MHz.
   11: Output mode, max speed 50 MHz

   and the upper two are

   In input mode (MODE[1:0]=00):
   00: Analog mode
   01: Floating input (reset state)
   10: Input with pull-up / pull-down
   11: Reserved
   In output mode (MODE[1:0] >00):
   00: General purpose output push-pull
   01: General purpose output Open-drain
   10: Alternate function output Push-pull
   11: Alternate function output Open-drain

   If you, for example, want a port to be output push-pull max speed 10MHz, the bits will be 0001 in binary. Four bits corresponds to one hexadecimal digit, 0x1 in this case. To set GPIOA in this mode you can write (in recent versions of libmaple)

   GPIOA->regs->CRL = 0x11111111; // Configure GPIOA[7:0]
   GPIOA->regs->CRH = 0x11111111;  // Configure GPIOA[15:8]

   (each hexadecimal digit corresponds to one port pin)

   To set GPIOA to input with pull-up enabled the four CR-bits will be 0b1000 which is 0x8 in hex and the ODR-register should be set to all 1's (zeros for pull-down).

   GPIOA->regs->CRL = 0x88888888;
   GPIOA->regs->CRH = 0x88888888;
   GPIOA->regs->ODR = 0xFFFF;

   So it's not that straight forward as on AVR's.

   Posted 4 years ago #
3. 

   robodude666
   Member

   Ah, that makes sense. I'll look at the manual first in the future :P.

   Each pin is controlled by 4 bits in the CRL/H registers. The lower two control the mode, which is whether it's an input or output, as well as what the output speed is in output mode. The upper two bits control the configuration related to how the pins drain/source current.

   So if both CRL and CRH are set to 0x33333333 then you'll have all 16-bits working as push-pull output @ 50MHz? When configuring a pin to input, is it required to also modify the ODR register to be LOW?

   Lastly, I also assume it's not wise to set the ENTIRE port to input/output, as some of the pins are being used already for something. I can see from the schematic that PA11/PA12 are being used for USB, PB2 is tied to ground for BOOT1, PC9 is connected to the BOOT0 button, and PC13/PC14 are used for the RTC. If I read the default configuration of these pins, could I write them back every time? (so that I simply set CRL/CRH every time instead of having to &/| to save instructions.) Would that work without interrupting their original configuration? In most cases, however, I'm fine with just the lower or upper 8, so I'll try to avoid using the half they reside in.

   -robodude666

   Posted 4 years ago #
4. 

   mbolivar
   LeafLabs

   robodude666,

   So if both CRL and CRH are set to 0x33333333 then you'll have all 16-bits working as push-pull output @ 50MHz?

   That's correct.

   Note also that if you don't like typing "->" (I sure don't), you can say e.g.

   GPIOA_BASE->CRL = 0x33333333;

   instead. I haven't checked, but since GPIOA_BASE is just a macro for ((gpio_reg_map*)0x40010800), it's possible that avoiding the indirection might allow the optimizer to do a little extra work.

   If I read the default configuration of these pins, could I write them back every time?

   I think that a better approach might be to lock the relevant control register bits through the port configuration lock register: GPIOx_LCKR in RM0008 (see sections 9.1.6 and 9.2.7), and GPIOx_BASE->LCKR in libmaple.

   Posted 4 years ago #
5. 

   gbulmer
   Moderator

   robodude666 -

   So if both CRL and CRH are set to 0x33333333 then you'll have all 16-bits working as push-pull output @ 50MHz?

   As I mention in the other thread http://forums.leaflabs.com/topic.php?id=774

   The 50MHz is the rise-time of the electrical signal, and not the rate that software can change the state of the GPIO pin. The theoretical maximum for toggling a pin is two store instructions, which must be at least 2 cycles at 72MHz, or 36MHz. In practice it is usually slower.

   mbolivar -

   I think that a better approach might be to lock the relevant control register bits through the port configuration lock register: GPIOx_LCKR in RM0008 (see sections 9.1.6 and 9.2.7), and GPIOx_BASE->LCKR in libmaple.

   Sneaky!-) I haven't tried that!

   Posted 4 years ago #

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