Oak FPGA Toolchain « LeafLabs Garden

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Oak FPGA Toolchain

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Started 5 years ago by gbulmer
Latest reply from gbulmer

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lanquarden
Member

Interesting read...

this week I came across MyHDL which made me think it might be good mentioning here. Everybody seems to agree that avoiding vendor tools for FPGA bit stream generation is hard. Going with this option it still means people have to write VHDL or Verilog. This can be difficult for people without previous experience even with extensive examples and documentation.

A short description from the website:
"The goal of the MyHDL project is to empower hardware designers with the elegance and simplicity of the Python language.

MyHDL is a free, open-source package for using Python as a hardware description and verification language. Python is a very high level language, and hardware designers can use its full power to model and simulate their designs. Moreover, MyHDL can convert a design to Verilog or VHDL. This provides a path into a traditional design flow."

It is already been used to map generated VHDL on FPGA as well as producing an ASIC. Through MyHDL users do not even need to know VHDL and can describe their hardware in a more familiar language.

http://www.myhdl.org

lq

Posted 5 years ago #
poslathian
LeafLabs

myhdl is a great project, I recommend it too. There is actually a small bundle of useful FOSS (free and open source) tools related to FPGA development, including some work on bitstream parsing (http://www.ulogic.org/trac). Icarus Verilog is good for simulation, and the lava language (haskell based HDL) is an interesting alternative to verilog. Im hoping to either watch or give a talk on the subject of FOSS and FPGA development at the Open Hardware Summit in september http://www.openhardwaresummit.org/.

Posted 5 years ago #
pagercam
Member

Any news on when we can expect Oak to be available?

Posted 5 years ago #
poslathian
LeafLabs

nope ;)

honestly, were working on it. But with so many maples in the field our priorities have shifted towards lib extensions, support, documentation, and building documenting some cool projects. Once Maple-side things stabilize a bit, and needs less nurturing, our attention will be refocused on getting Oak out the door. On the bright side, the delay has allowed us to secure access to some new chips for oak (still spartan and stm32 series...) which is awesome. More details later...

Posted 5 years ago #
pagercam
Member

any more details???

Posted 5 years ago #
mbolivar
LeafLabs

oak is still being actively developed; components have been placed, and traces are being laid out. you can view development logs on the oak github repo:
https://github.com/leaflabs/oak

Posted 5 years ago #
mabl
Member

There has been no git activity on maple native for two months now. Is Oak supposed to be released before Native? Is there any timetable out? I'm desperately waiting for the native...

Posted 5 years ago #
poslathian
LeafLabs

Native is out for prototyping! Fingers crossed, were shooting to get it on sale in time to arrive at your doorstep by christmas. We had an annoying but AWESOME bug in the last prototype which required manually *skywiring* (go bryan) an entire 30 pin RAM bus to get everything to work. Perhaps Ill throw a picture of this up on the blog.

Posted 5 years ago #
gbulmer
Moderator

So when is Oak intended to be available?

Posted 5 years ago #
josheeg
Member

I looked into a lot of Myhdl and python created hdl and matlab created hdl. I tried using scilab or octave but the hdl link to eather of thowse is not avalable.

The tool I did use was xilinx FPGA schematic drawing program and was going to make larger chip like modules from the drawn gates.
You can see how if HDL files can be made into a schematic block then assebled together into schematic like diagrams a layored herarchal open source tool like kicad with its scriptablility for creating its schematic symbols & possibility for logic design I don't want to say geda and gnu cap for making digital logic simulatable then let it get packed into a fpga.

Schematic versioning can get to be a pain. do the newest versions apaear with different color text?

But kicad does have a herarchal design so if its netlist & standard and or etc a hand full of basic gates have the HDL logic behind them it might empower the linux community.

Posted 5 years ago #
josheeg
Member

also I played with the open fpga design from gadgetfactory.org it even allowed for a arduino to be simulated.
So you had pin configurable arduino with schematic fpga design using xilinx software.

Posted 5 years ago #
josheeg
Member

Another way to look at things is if a schematic entery program geda or kicad I like kicad. Had basic logic and and or gates 2-3 of its libraries contained HDL info.
Then something to parse the open netlist format kicad produced. To link the schematic drawings of the and and or gates and herarchy from a upper level sheet to a lower level sheet that looked like a chip sorta. Then verilog hdl could be output and that tool is open source as a simulator.
Then you would use a vendor compiler.
At least it gets it most of the way useable from high level to lower level rather than lower level to higher level.

Posted 5 years ago #
poslathian
LeafLabs

Ill have to check out gadgetfactory.org, that sounds interesting. icarus is a pretty successful open source verilog simulator. Im not sure how I feel about the python/c/c++/haskell -> verilog compilers. At least in the case of the c->verilog, performance is way down from hand coded verilog. Haskell->verilog has a decent open source project called lava, and a struggling commercial language called bluespec which is something like haskell+system verilog based around a programmers model of "guarded atomic actions" which is popular in the multicore world. I found it cumbersome.

visual editing seems like a nice approach, but pro's really want to work with the keyboard, not the mouse - no one "writes" programs by "compiling" uml diagrams. Its really an open question of what direction to push FPGA devel in, and by the length of this topic I think its one that everyone is pretty excited to work on.

Posted 5 years ago #
josheeg
Member

It is a tough comparison next time you want to draw a circuit do you open eagle cad the non free and open source thingy. Or do you wine about using free and open source kicad.
If you do then you want what you think is the easier way out. But if you like to type and think you can get that all correct and do not have a mouse plugged into your computer then shure type out the netlists I am shure it is scriptable...

It took a very long time to write in the schematic capture schematic of something that might load info into my analog to digital converter.

But it was some ands and or gates and shift registers and If I was to implement the BSS code to decode mucle signals it would be years. ... now if that was written in HDL it would be even longer... HDL makes asm look like something high level.
Shure you can generate ands and or modules in hdl but if you had the ability to connect them by netlist by writing the netlist or drawing the modules. You had a choice.

I agree UML models do not compile... I looked.... But schematics can connect to the board files and they can check eatchother.

Also to say a schematic is not useful there used now and someone with a electronics background but not a perticular language can fallow the schematic.

Also consider it documenting your code at the same time and how many bugs would be missed using a aplication or some other script to generate the schematic symbols in kicad to make it faster it is a toolsuete that is allready open source. So when you say what is faster this can be scripted and typed and graphical and document itself in pictures that are herarchal. Also the local and global pins etc are allready there in kicad so your structure is there.

Also if the schematics were herarchal like in kicad then the HDL netlists woudl be like functions and classes with global and local pins like kicad has.

Lava is described as netlisting using a text language so it is like nitting together a netlist using text once again.

Posted 5 years ago #
pra
Member

This topic thread has been quiet for a while, so I thought I would try to liven it up.

I got my first maple (I now have 4 of them) a few weeks ago and when I read that LeafLabs plans a Cortex M3 and Xilinx Spartan 3E FPGA on the same board (Oak) I got very excited about the prospects. To speed the learning curve and to get the old juices flowing about possibilities, I now have a Nexys 2 FPGA development board from Digilent (yah, I know the ChipKit people) with a Spartan 3E 500K gate FPGA in a 320 pin package.

I have just started learning and playing with the development board using Xilinx's free WebPack toolkit and I think my experiences as I progress with this endeavor may be interesting and useful for thread readers.

First off, a bit about myself. I am a semi-retired systems engineer who lives in a cabin on a mountain in WV (Almost Heaven West Virginia). Not the greatest place for high speed internet access; I'm about 500 meters beyond the max length of a DSL connection, and that combined with an ISP service oversold and underpowered bandwidth wise from the local communications company, leads to iffy and unreliable DSL connection. I have been in the IT industry for more years than I care to remember (> 40) and still work part-time as a security consultant to one of the nation's largest defense contractors.

I started as a hardware field engineer on mainframes back in the late 1960s. Its amazing that the maple can probably outperform that original system (a Univac 494) which at the time ran the real-time reservation system for Australia's domestic airline, maybe many times over. If I still had the logic diagrams (and the patience), I could probably rebuilt that mainframe into my FPGA development board today with most of the capacity of the FPGA to spare. The capability and potential of what we have today is just incredible. Since those times I moved into software development, operating systems design, and eventually consulting.

Moving onto WebPack. Some of the earlier comments in this thread regarding vendor tool chains; the 3.8 gigabyte download and my internet connection; and MS Windows only install had me a little skeptical and nervous. I used a Mac development environment. I run Windows 7 in a Parallels VM for windows stuff and I realize there are some useful tools out there that will only run in windows. Anyway, the WebPack download and install from Xilinx was smooth and painless. I downloaded their latest version (at the time) 13.1. They have a download manager that handled without trouble the restarts caused by two lost connections during 3 hour download. The install was easy and smooth, and registering and licensing of WebPack (free perpetual license) made simple via interactions with the Xilinx License Manager website.

WebPack is a complex package of many different toolsets, but Xilinx has done a good job of knitting them all together using the ISE Navigator. Given the high version number, I don't imagine this has been a very easy or fast evolutionary process, but what they have today is pretty together and cohesive from a new user perspective. For the best perspective on the FPGA development process I recommend downloading the latest version of theSpartan3E_UserGuide from Xilinx. Starting at Chapter 13 "Using ISE Design Tools" is an amazing well-written (no engineer speak) and coherent walkthrough of the design and implementation process and how to accomplish it using Xilinx ISE tools, including WebPack.

I think that will do it for now; as I progress further, I will add updates. The feeling of accomplishment from installing something as simple as a 8 input XOR circuit, and watching the Led turn on and off correctly as I set/reset switches on the Dev board is incredible. Off now to learn more about VHDL :-)

Posted 4 years ago #

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