How about something like this?
#define HSO_FREQ 8000000UL
#define RCC_PLLMUL RCC_PLLMUL_9
#define CLOCK_SPEED_HZ (HSO_FREQ * RCC_PLLMUL)
#define CLOCK_SPEED_MHZ (CLOCK_SPEED_HZ / 1000000UL)
#define RCC_AHB_SYSCLK_DIV RCC_AHB_SYSCLK_DIV_1
#define RCC_APB1_HCLK_DIV RCC_APB1_HCLK_DIV_2
#define RCC_APB2_HCLK_DIV RCC_APB2_HCLK_DIV_1
#define CYCLES_PER_MICROSECOND CLOCK_SPEED_MHZ
#define SYSTICK_RELOAD_VAL (CLOCK_SPEED_HZ / 1000 - 1) /* takes a cycle to reload */
#define PCLK1 (CLOCK_SPEED_HZ / RCC_APB1_HCLK_DIV)
#define PCLK2 (CLOCK_SPEED_HZ / RCC_APB2_HCLK_DIV)