Here a little related info:
Originally there were two languages related to ASIC development and circuit design, verilog and vhdl. Verilog was the SIMULATION language and VHDL was the SYNTHESIS language. Eventually, someone verilog became synthesizable as well, thus making VHDL somewhat obsolete. However, the large institutionalized developers stuck with it for...inertial reasons (or so Ive been told). VHDL is super common in aerospace and military related work. Verilog is more common in consumer work - at Analog Devices we used verilog.
Later on variants and extensions on verilog became available, system verilog and bluespec (system verilog+haskell+other stuff), and these have expensive compilers. However the sugar-free verilog compilers are still free (as in gratis, not as in libre) from the major FPGA manufacturers. There are some libre packages for simulating verilog, such as icarus.
Personally, I use verilog. Jess uses VHDL. It has been my intention to make Oak verilog-centric, but that debate hasnt really come to a head yet.