I have updated the F3-port to support more chips.
Theoretically all the currently available STM32F301/302/303 chips should be supported:
STM32F301xx:
-STM32F301K6
-STM32F301K8
-STM32F301C6
-STM32F301C8
-STM32F301R6
-STM32F301R8
STM32F302xx:
-STM32F302K6
-STM32F302K8
-STM32F302C6
-STM32F302C8
-STM32F302CB
-STM32F302CC
-STM32F302R6
-STM32F302R8
-STM32F302RB
-STM32F302RC
-STM32F302VB
-STM32F302VC
STM32F303xx:
-STM32F303K6
-STM32F303K8
-STM32F303C6
-STM32F303C8
-STM32F303CB
-STM32F303CC
-STM32F303R6
-STM32F303R8
-STM32F303RB
-STM32F303RC
-STM32F303VB
-STM32F303VC
https://github.com/ventosus/libmaple/tree/F3
Apart from the STM32F303CB and STM32F303CC that I have thoroughly tested so far, I have a ST NUCLEO-F302R8 since some days.
http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF259999
To use the nucleo with the F3-port, just compile for
[code]
BOARD=F302R8
MEMORY_TARGET=jtag
[/code]
mount the nucleo as USB mass storage, copy the bin/F302R8.bin to the mass storage, unmount it and the sketch should be running. The included ST/Link works out of the box with OpenOCD and GDB.
My nucleo was shipped without an oscillator, as libmaple by default assumes that there is an external oscillator and will block until it's up and running, the following patch needs to be applied, though:
[code]
diff --git a/wirish/boards.cpp b/wirish/boards.cpp
index a693fa6..e97259d 100644
--- a/wirish/boards.cpp
+++ b/wirish/boards.cpp
@@ -122,8 +122,8 @@ static void setup_clocks(void) {
RCC_BASE->CIR = 0x00000000;
// Enable HSE, and wait until it's ready.
- rcc_turn_on_clk(RCC_CLK_HSE);
- while (!rcc_is_clk_ready(RCC_CLK_HSE))
+ rcc_turn_on_clk(RCC_CLK_HSI);
+ while (!rcc_is_clk_ready(RCC_CLK_HSI))
;
// Configure AHBx, APBx, etc. prescalers and the main PLL.
diff --git a/wirish/stm32f3/boards_setup.cpp b/wirish/stm32f3/boards_setup.cpp
index 6984419..b1a4991 100644
--- a/wirish/stm32f3/boards_setup.cpp
+++ b/wirish/stm32f3/boards_setup.cpp
@@ -59,7 +59,7 @@ namespace wirish {
namespace priv {
static stm32f3_rcc_pll_data pll_data = {.pll_mul=BOARD_RCC_PLLMUL, .pcl
- __weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data};
+ __weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSI_DIV_2, &pll_data};
__weak adc_prescaler w_adc_pre = ADC_PRE_PCLK_DIV_1;
__weak adc_smp_rate w_adc_smp = ADC_SMPR_181_5;
[/code]
