@feurig, usually if library part causes such problems I'm just changing package in library editor. In most cases it's enough to move part or all drawings at tPlace layer to tDocu layer. Of course, things moved to tDocu layer will be missing in resulting silk screen.
Community rework of standard maple and maple mini.
(181 posts) (14 voices)-
gbulmer
Moderatorfeurig - I have been using Seeeeeeedstudios Eagle Design Rules (http://www.seeedstudio.com/depot/datasheet/Fusion%20eagle.zip).
The only errors are due to a 'bridge' (two touching pads), which can be safely ignored as its just one piece of copper.I have loaded up the OSHPark Eagle Design Rules (http://oshpark.com/LaenPCBOrder.dru)
I get a *LOT* of Stop Mask errors. Are you saying that OSHPark clean them up for me?
OSHPark put a Stop Mask on *EVERY* via. That damages some of the silk screen. Do you know if there is a way to get 'tented vias'?
Unlike Seeeeed, OSHPark DRU complains about vias within pads. I want to put vias within the regulator's 'Tab' pin pad to improve heat transfer to the bottom copper ground plane. Do you know if OSHPark will reject the PCB with those?
I have emailed laen but not received a reply yet.
BTW - Is there already a set of Creative Commons logos in an Eagle library?
Edit: Also where is the 'Open Source Hardware' logo Eagle libraryPosted 2 years ago # -
gbulmer
ModeratorSiy - I apologise for being unclear.
The issue is not how to get Eagle to make tented vias.
The issue is the OSHPark DRU file sets the mask limits so that no vias are tented.
So I'd like to know does OSHPark demand or enforce that mask limit? If not what are the mask limits for tented vias which their service supports?Posted 2 years ago # -
siy
Member@gbulmer, sorry for skipping explanation, it looked too obvious to me. From the technology perspective this parameter sets the size of smallest feature which can be reproduced at solder mask layer. In other words, it defines lower limit. But nothing may prevent you to increase it, because everything larger can be reliably reproduced as well. It's like trace/space limits - if process allows you to produce boards with 6mil trace/space, there is no way to enforce you to use this limit if you decide to make 8mil trace/space design. So, I believe that you can safely increase this limit and have vias tented.
Posted 2 years ago # -
gbulmer
ModeratorSiy - Thank you for the post. I assume my question is still not clear because your response does not address my concern.
I am assuming that the Eagle DRU file from OSHPark sets the Masks->Limit to 0mil for a reason.
This may be incorrect. However, there are several possible explanations for this 0mil limit, and several approaches to resolving my issue. I am trying to find out which approaches apply to the OSHPark PCB service.While nothing prevents me setting the Mask->Limit to any value, that is not the question.
The real question is about printing silk screen across vias and getting acceptable results.
Silk Screen Text may be printed onto the unmasked metal, or it could be onto the solder mask. I'd prefer it to be on solder mask for aesthetic reasons, but it isn't essential.
I want the silk screen text to be legible, in the right place on the board. Currently some of the text needs to cross vias. Currently the OSHPark DRU file signals all silk screen across vias as errors.
To produce the board without errors, and without changing the OSHPark DRU file, I could move the text, which might cause the text to be less helpful and clear, or I could try to move vias, which is awkward.
I would like to know if there is another approach to getting clear silk screen text acoss vias on OSHPark boards.
I could set the Masks->Limit > via drill size, but I don't know at what size that might fail. I have seen articles where the via drill size should be at or below 0.35mm for tenting, and I think I have (somewhere) a PCB makers spec which set the tented via drill size at 0.3mm.Hence, the analogy with minimum track and space does not necessarily apply to solder mask tenting. It is not a question of the level of detail that can be reliably produced when making the solder mask because there are more facts needed about the OSHPark process.
I want to know:
1. Will the silk screen be 'trimmed' to remove any silk screen over un-masked 'copper'? If the answer is 'No, silk screen is not trimmed', then will silk screen be printed across unmasked vias with reasonable results? If the answer is 'yes, silk screen is printed across unmasked 'copper' with good results', then I don't need to do anything. I can leave the OSHPark DRU file unchanged, and I am happy to get some boards made.
2. If the answer to 1 is "No you won't get the silk screen printed adequately" then what are the robust limits of drill diameter across which tenting and silk screen printing works adequately well? These limits must be small enough that the tenting will be unlikely to sag to a depth where silk screen printing becomes illegible. That drill diameter is the value that should be entered into the DRU Masks->Limit field.It may be that OSHPark have never had reliable results from silk screen printed across tented vias even on the smallest drill, and hence the Masks->Limit is 0mil. It may be that text prints well across 'metal' so the designer is expected to adjust the silk screen text so that it isn't rendered illegible by the via drill hole. It may be that the chemicals used for the ENIG (gold) finish leak through pin-holes in the solder mask, get trapped in the via holes, lead to problems, and so no hole can be covered by solder mask, though the copper of the via can be covered; however that might be too complex to describe in Eagle and hence the designer needs to do this by hand. It may be that silk screen with some ratio of stroke thickness to via diameter prints well across ENIG-finished metal, but that is too complex to define in an Eagle DRU file. I don't need speculation, I need facts or evidence about OSHPark.
As an aside, it is not necessarily true that larger sizes of tented via drill holes than a minimum limit can meet these criteria.
Lets imagine the following:
1. Set Mask->Limit to 21mm
2. Create a 20mm diameter via
3. Print some text, for example 'Tented Via', on the silk screen layers across the hole of the via
4. Get the board made at OSHPark
Was the board rejected? Was the silk screen text printed? Was it legible? Or has the tenting collapsed, or is the text not clear and legible? Is the text on tented mask easily damaged? These all need to be answered appropriately for the result to be of use.Edit: To minimise further confusion, please do not reply unless you have experience or detailed knowledge of the OSHPark PCB Service. Either explain an approach to printing text across vias that OSHPark can produce, or explain what can be produced by OSHPark PCB service so that I can figure out an approach.
Posted 2 years ago # -
siy
MemberMust admit that I'm also interested in authoritative information. PCB technologies are one of my areas of deep interest and if your guess is correct OSH Park must be using some very unusual processes and materials for solder mask and silk screen. Since Mask->Limit applies not only to vias but to the SMD's as well, it may mean that OSH Park has technology able to reproduce such a small features. So, I'll be happy to know more details about these processes and materials.
P.S. While I'm really interested in PCB technologies, I'm sure that zero value in Mask->Limit field is either a mistake or left at designers' discretion. Widely used two component LPI solder masks and inks have no problems with proper tenting of small (0.3-0.4mm) vias and silk screen over them. But, as I've mentioned, I'm really interested to get know in authoritative answer.
Posted 2 years ago # -
gbulmer
ModeratorLaen has replied and says "Any drill hit under about 20 mils (0.5mm) should be just fine with tenting. "
So I can change all vias to 0.5mm, and that should fix all my stop mask errors. Yipeee!
All I need now are the Creative Commons and Open Source Hardware Eagle devices.
Would someone please point me at them?
I've found bit-map conversion version, but I'd much prefer vector forms.EDIT: I have a small library for the thru-hole USB-mini socket with two different package footprints. One uses a milled slot for the attachment lugs. The other uses two drill holes, with a 12mil gap between edges, the material between holes will need further finishing. I have been defaulting to the slot, but drill holes might be easier to get made. Folks may want to choose the appropriate footprint when they make boards.
EDIT 2: Laen has come through with more good information and ideas. So I am updating the USB Mini footprint.
Posted 2 years ago # -
gbulmer
ModeratorI've released the first 'Orone-mini' https://github.com/gbulmer/openstm32hw
Features:
- 1206 parts,
- 0.8" header pin spacing (0.2" wider than Maple-mini),
- 2pin Molex for external power
- Power-on LED
- reworked USB
- supplies 'av+' from the main regulator,
- polyfuse protected USB host power
- single-sided SMD, with thru-hole for 'top' components (USB socket, buttons, LEDs and power socket)
- uses USB footprint based on Laen's suggestion for Molex thru-hole socket, which should be plated, and require little finishing
- larger 'top' silk screen for pin labels and text
- larger 'bottom' silk screen with component designations to help DIY assembly
- passes OSHPark and Seeedstudio Design Rules (except for Eagles inability to support a 'bridge', and I believe these errors can be ignored)I'll add a blog article and the other boards (e.g. 0.6: spacing) when I get some time.
I think this is as good as I can do, so all defects are 'learning opportunities' and I'd very much appreciate feedback.
I will probably send the gerbers to OSHPark early next week, when I expect to have at least one other board ready-to-go.Edit: I need to upload my USB-mini footprint library in case anyone wants to try one of the other methods for making the holes for the USB socket's 'lugs'.
Thanks to everyone here, especially Siy, for help and encouragement. Thanks to Pete Harrison and Mark Rafter who provided 'in-flight' discussions, advice and support, Keith and Pete at Tekwizz who provided a valuable sounding-board and feedback, Tony Wilcox, Chris Evans, and David Hannaford for sharing expertise. Thanks especially to LeafLabs for Maple-IDE and the Maple-mini. Thanks to everyone I've not mentioned, and please ping me if I should have added an explicit mention.
Of course, all defects are mine.
Posted 2 years ago # -
gbulmer
Moderatorfeurig - Thanks :-)
There are three 'defects' that I am aware of:
1. Clearance and overlap errors from a 'bridge' used to separate ground around the crystal. Approved.
2. Overlap errors from 'thermal' vias through the regulators ground tab-pin. Approved.
3. Overlapping drill holes for the USB-mini socket's thru-hole lugs. Laen suggested this approach. Approved.
Any other defects are unknown to me :-)
So all feedback gratefully received!I'll be at MINOS 2013 at the weekend http://www.rhul.ac.uk/computerscience/events/eventsarticles/minos2013conference.aspx
I have a variant for 0.6" header spacing, practically identical to Maple-mini, which I'm hoping to progress to release Monday.
I'm currently thinking of getting PCBs for two designs made by OSHPark.Posted 2 years ago # -
@gbulmer, thanks, this is awesome, I'm keen to test this.
>> I need to upload my USB-mini footprint library...
This would be great, indeed. I have to increase all the annular rings of plated through holes to at least 0.125mm to get the design through the online DRC at eurocircuits.com. For the vias its straight-forward to do, but to alter the pads on the USB connector, eagle seems to need the library file.
Posted 2 years ago # -
gbulmer
Moderatorventosus - ">> I need to upload my USB-mini footprint library..."
Okay.
" I have to increase all the annular rings of plated through holes to at least 0.125mm to get the design through the online DRC at eurocircuits.com. ... "
I try to route using 0.7mm vias, then shrink in the late stages, so most of the vias should have plenty of space around them to increase the annular ring.
"... but to alter the pads on the USB connector, eagle seems to need the library file."
Okay, I've pushed that Library. Please note, it isn't tested either.
Edit: ventosus - you might need to check with eurocircuits to discover the 'right' way to make the USB footprint 'slots'.
The library contains three footprints:
1. Three overlapping holes - OSHPark
2. Two non-overlapping holes which I'd expect most PCB manufacturers to do. This needs some finishing (e.g. with a craft knife) to remove the web of PCB material between the two holes.
3. Milled slot. I didn't want to use this at OSHPark because slots are not plated, and I think plating might give extra surface for the solder to attach to.
You can use Eagles 'part substitution' and swap the USB footprint on the PCB. The tracks will be unaffected, so it is a very quick change to make.
The top silkscreen should combine tNames and tPlace to get the assembly information printed onto the PCB.Edit 2: There was a defect; the segregated ground plane under the ADC signals was not connected to 'av-'. Fixes pushed to github.
Posted 2 years ago # -
gbulmer
ModeratorI've uploaded a Bill of Materials (BoM) for RS components and Farnell, as both pdf and a CSV spreadsheet.
The NUF2042XV6 part is only stocked by Future Electronics so that column only has one item.The BoM contains the parts for the already released 0.8" spacing, 1206-size parts. I've organised it so that the common part-values (but not part numbers) for the 0.6" spacing 0805 comes first. This is probably pointless, and I'll likely revert to a simpler list when I update it.
Many of the parts are generic, or have alternatives, so I've given several part numbers.
I have not found a 100uF capacitor that I am happy with.
I think it needs to be at least 16V if it's intended to withstand 9V external power on Vin.Posted 2 years ago # -
gbulmer
ModeratorWhile compiling the Bill of Material (BoM) the cost of C1, 100uF 16V (1206-size) was a but crazy (£3.73 for example).
So I looked for a reasonable price C1 (£0.30), and swapped the 1206 (3216 metric, 3.2x1.6mm), for a 2917 (metric 7343 7.3x4.3mm).
I've re-routed, and I'll check it in as a new variant on Monday, with a new BoM.
Posted 2 years ago #
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