LeafLabs Garden » User Favorites: jbaker

LeafLabs Garden » User Favorites: jbaker 4229 A place to share, learn, and grow... en-US Fri, 22 Jan 2016 00:15:33 +0000 http://bbpress.org/?v=1.0.2 <![CDATA[Search]]> q http://forums.leaflabs.com/search.php jbaker on "Running Maple on a custom board with 12MHz crystal" http://forums.leaflabs.com/topic.php?id=74329#post-105379 Sun, 11 May 2014 20:32:59 +0000 jbaker 105379@http://forums.leaflabs.com/ I did get code running with the JTAG target and no bootloader, but I'm not sure how to verify the frequency of SYSCLK from there. jbaker on "Running Maple on a custom board with 12MHz crystal" http://forums.leaflabs.com/topic.php?id=74329#post-105377 Sun, 11 May 2014 14:27:51 +0000 jbaker 105377@http://forums.leaflabs.com/ I have a board with an F103CBT6 that I want to run the Maple bootloader on. I loaded the bootloader .bin file with an ST-LINK/v2 and that worked but the IDE wasn't seeing the board when I tried to upload via USB. I then tried loading the .bin out of the temp directory and that didn't work either (crystal not oscillating and code not running as in <a href="http://forums.leaflabs.com/topic.php?id=74271)" rel="nofollow">http://forums.leaflabs.com/topic.php?id=74271)</a>. I didn't happen to scope the crystal with the bootloader running. At this point, I realized that I made the mistake of using a 12MHz crystal instead of the 8MHz used on the Maple proper. My current theory is that it doesn't like having PLLMUL set to 9. How do I go about changing the configuration for the correct PLLMUL value to get a 72MHz clock? I assume I need to add a new board definition etc but I can't find where it sets PLLMUL. gbulmer on "Porting libmaple to STM32L1 -- mystery hex values in register maps?" http://forums.leaflabs.com/topic.php?id=1227#post-7431 Sat, 24 Dec 2011 10:28:58 +0000 gbulmer 7431@http://forums.leaflabs.com/ jbaker - I'm glad to help. I did look at the RM0008, and I think I would change: <pre><code>#define ADC_CR2_JEXTSEL (0x7000) #define ADC_CR2_EXTSEL (0xE0000)</code></pre> to <pre><code>#define ADC_CR2_JEXTSEL_OFFSET (12) #define ADC_CR2_JEXTSEL (0b111 << ADC_CR2_JEXTSEL_OFFSET) #define ADC_CR2_EXTSEL_OFFSET (17) #define ADC_CR2_EXTSEL (0b111 << ADC_CR2_EXTSEL_OFFSET)</code></pre> because there are a bunch of values which will need to be extracted, and so the ADC_CR2_..._OFFSET values will likely be useful. I'd probably use 0x7 rather than 0b111 if I were unsure which C compiler might be used. jbaker on "Porting libmaple to STM32L1 -- mystery hex values in register maps?" http://forums.leaflabs.com/topic.php?id=1227#post-7425 Fri, 23 Dec 2011 01:38:14 +0000 jbaker 7425@http://forums.leaflabs.com/ You got it -- I've never seen the values hardcoded in a macro like that, so when I saw it alongside the other definitions using shifts I figured it was something weirder going on than just different styles within the same file, thanks. gbulmer on "Porting libmaple to STM32L1 -- mystery hex values in register maps?" http://forums.leaflabs.com/topic.php?id=1227#post-7418 Wed, 21 Dec 2011 22:34:56 +0000 gbulmer 7418@http://forums.leaflabs.com/ jbaker - I'm not sure what you are asking. Would you try to explain the issue a bit more? BIT(7) is the same as (01 << 7) 0x7000 is the same as (0x7 << 12) I think it is partly personal preference on how it is done I might do: <pre><code>#define ADC_SMPR1_SMP17 (0b111 << 7*3) #define ADC_SMPR1_SMP16 (0b111 << 6*3) #define ADC_SMPR1_SMP15 (0b111 << 5*3) #define ADC_SMPR1_SMP14 (0b111 << 4*3) #define ADC_SMPR1_SMP13 (0b111 << 3*3) #define ADC_SMPR1_SMP12 (0b111 << 2*3) #define ADC_SMPR1_SMP11 (0b111 << 1*3) #define ADC_SMPR1_SMP10 (0b111 << 0*3)</code></pre> or something similar, to show that the register/word looks like an array of 3 bit values. But I might use either (0x7 << 12) or (0x7000) or even (0b111000000000000) for a specific field in a complex set of register fields. Which I use would likely be influenced by the way the documentation describes the fields. The layout of peripheral register fields are all described in RM0008: <a href="http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/REFERENCE_MANUAL/CD00171190.pdf" rel="nofollow">http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/REFERENCE_MANUAL/CD00171190.pdf</a> Sorry I can't be more help. (Full disclosure: I am not a member of LeafLabs staff.) jbaker on "Porting libmaple to STM32L1 -- mystery hex values in register maps?" http://forums.leaflabs.com/topic.php?id=1227#post-7412 Wed, 21 Dec 2011 03:38:06 +0000 jbaker 7412@http://forums.leaflabs.com/ I'm working on a port of libmaple for the STM32L1 for a dev board I'm working on, and I'm running into some mystery hex values in the header files that I can't make heads or tails of. For example, the definitions for Configuration Register 2 in adc.h: <code> #define ADC_CR2_ADON BIT(ADC_CR2_ADON_BIT) #define ADC_CR2_CONT BIT(ADC_CR2_CONT_BIT) #define ADC_CR2_CAL BIT(ADC_CR2_CAL_BIT) #define ADC_CR2_RSTCAL BIT(ADC_CR2_RSTCAL_BIT) #define ADC_CR2_DMA BIT(ADC_CR2_DMA_BIT) #define ADC_CR2_ALIGN BIT(ADC_CR2_ALIGN_BIT) #define ADC_CR2_JEXTSEL (0x7000) #define ADC_CR2_JEXTTRIG BIT(ADC_CR2_JEXTTRIG_BIT) #define ADC_CR2_EXTSEL (0xE0000) #define ADC_CR2_EXTTRIG BIT(ADC_CR2_EXTTRIG_BIT) #define ADC_CR2_JSWSTART BIT(ADC_CR2_JSWSTART_BIT) #define ADC_CR2_SWSTART BIT(ADC_CR2_SWSTART_BIT) #define ADC_CR2_TSEREFE BIT(ADC_CR2_TSEREFE_BIT) </code> EXTSEL and JEXTSEL are multi-bit settings so I understand why it wouldn't be a single bitshift, but where are those values coming from? In this case, they're both 3-bit values. The sample time registers are all 3-bit values as well, but they're all defined like this (which does make sense): <code> #define ADC_SMPR1_SMP17 (0x7 << 21) #define ADC_SMPR1_SMP16 (0x7 << 18) #define ADC_SMPR1_SMP15 (0x7 << 15) #define ADC_SMPR1_SMP14 (0x7 << 12) #define ADC_SMPR1_SMP13 (0x7 << 9) #define ADC_SMPR1_SMP12 (0x7 << 6) #define ADC_SMPR1_SMP11 (0x7 << 3) #define ADC_SMPR1_SMP10 0x7 </code>