http://forums.leaflabs.com/topic.php?id=1298 A place to share, learn, and grow... en-US Fri, 22 Jan 2016 00:13:56 +0000 http://bbpress.org/?v=1.0.2 q http://forums.leaflabs.com/search.php http://forums.leaflabs.com/topic.php?id=1298#post-7831 Sun, 22 Jan 2012 19:13:16 +0000 gbulmer 7831@http://forums.leaflabs.com/ <p>I have found the answer to my own question!</p> <p><a href="http://www.ethernut.de/en/documents/arm-inline-asm.html" rel="nofollow">http://www.ethernut.de/en/documents/arm-inline-asm.html</a></p> <p>says in the section "Register Usage":<br /> r10 sl Stack limit<br /> r11 fp Argument pointer<br /> r12 ip Temporary workspace<br /> r13 sp Stack pointer<br /> r14 lr Link register Workspace </p> <p>I will leave the question in case anyone else is puzzled.</p> <p>Edit: Pete Harrison found<br /> <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042d/IHI0042D_aapcs.pdf" rel="nofollow">http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042d/IHI0042D_aapcs.pdf</a><br /> Which says:<br /> "Register r12 (IP) may be used by a linker as a scratch register between a routine and any subroutine it calls (for details, see §5.3.1.1, Use of IP by the linker). It can also be used within a routine to hold intermediate values between subroutine calls."</p> <p>ala42 Thank you very much for looking. I apologise for taking your time, I 'd written this but forgot to post (due to a food-shortage distraction). </p> http://forums.leaflabs.com/topic.php?id=1298#post-7829 Sun, 22 Jan 2012 18:52:28 +0000 ala42 7829@http://forums.leaflabs.com/ <p><a href="http://www.complang.tuwien.ac.at/forth/gforth/Docs-html/ARM-Assembler.html" rel="nofollow">http://www.complang.tuwien.ac.at/forth/gforth/Docs-html/ARM-Assembler.html</a> says:<br /> Registers are specified by their names r0 through r15, with the aliases pc, lr, sp, ip and fp provided for convenience. Note that ip means intra procedure call scratch register (r12) and does not refer to the instruction pointer.<br /> Also see <a href="http://www.cl.cam.ac.uk/teaching/2002/CompDesig/lecture4.pdf" rel="nofollow">http://www.cl.cam.ac.uk/teaching/2002/CompDesig/lecture4.pdf</a> </p> http://forums.leaflabs.com/topic.php?id=1298#post-7826 Sun, 22 Jan 2012 17:42:15 +0000 gbulmer 7826@http://forums.leaflabs.com/ <p>I've been reading the ARM assembly language output produced by arm-none-eabi-gcc (the gcc compiler than comes within the Maple IDE).</p> <p>I thought registers are either r0 to r15, or<br /> Stack ptr register: sp<br /> Frame ptr register: fp<br /> Link (return) register: lr<br /> Instruction Pointer/Program Counter: ip</p> <p>For example, those are the meanings in microcross.com/GNU-ARM-Assy-Quick-Ref.pdf</p> <p>Irritatingly, the documentation at CodeSourcery for as, the assembler says:<br /> "9.3.2.3 Register Names<br /> *TODO* Explain about ARM register naming, and the predefined names."</p> <p>So I had thought "ip" was the name of the Instruction Pointer/Program Counter, but can't find a definitive answer.</p> <p>But ip = program counter that makes these weird:<br /> cmp ip, #32 // I think this is position independent code, or relocatable code<br /> ...<br /> ...<br /> movs r5, #1<br /> ...<br /> and ip, ip, r5 // "The definitive guide to the Cortex-M3", ed 2, says this is illegal</p> <p>even these seem a bit odd:<br /> mov ip, r4 // a computed branch?</p> <p>str ip, [r6, #12] // store the value in ip to a peripheral pin address?</p> <p>add ip, ip, #2 // skip a thumb instruction?</p> <p>I am very inclined to believe ip is not the program counter, but what else might it be?<br /> Can anyone confirm that ip is the program counter, or tell me the correct meaning?</p> <p>Edit: I am pretty sure some of the assembly language instructions in the program are illegal if ip is the program counter. </p>